ASIC /FPGA - Design & Verification Engineer
ASIC /FPGA - Design & Verification Engineer - Melbourne, FL /Cedar Rapid,Iowa- Remote - $120K/YR - $160K/YR depending on exp ( ASIC/FPGA Design & verification exp, SV/UVM exp - candidate needs to have strong verification exp) - need to travel once in a quarter.
- 1 positions- GC/USC only - Recommended Skills Computer Engineering System Programming Software Engineering Tcl (Programming Language) C+
(Programming Language) Algorithms Estimated Salary: $20 to $28 per hour based on qualifications.
- 1 positions- GC/USC only - Recommended Skills Computer Engineering System Programming Software Engineering Tcl (Programming Language) C+
(Programming Language) Algorithms Estimated Salary: $20 to $28 per hour based on qualifications.
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